Conditions
Language
- English
Experience
Minimum level: Experienced ProfessionalJob Description
Join the SCE team within NXP, a world leader in security and mobile payment applications. Design cutting-edge RF/analog systems in advanced process nodes (40nm, 28HPC, 22FDX, …). Collaborate across organizational and geographical boundaries as a System Digital Design Engineer.
Responsibilities
- Design, develop, test and debug digital electronic circuits in Verilog/SystemVerilog.
- Work closely with design engineers to ensure that all digital design blocks meet performance, area and power requirements
- Collaborate with verification team members to ensure that all digital designs are thoroughly tested and verified
- Contribute to the development of analog behavioral models for use in digital simulations
- Work on multiple power and clock domains and high-speed digital design
- Develop digital signal processing functions such as sample rate converters, FIR filters, delta-sigma modulators, clock recoveries,…
Job Description
The goal of the SCE (Secure Connected Edge) team within NXP is to become the leader in its market by leveraging its unique portfolio of IP from NFC and Secure Elements, NFC and UHF tags, Wi-Fi, UWB and Bluetooth products to deliver solutions that are better than the sum of its parts. As a System Digital Design Engineer, you will be involved in the entire activity around the definition, design, and verification of our digital islands. You have excellent communication skills and proven ability to collaborate across organizational and geographical boundaries. The role might also involve communication with key customers for detailed reviews.
Qualifications
- Proficient in Verilog/System Verilog RTL coding
- Firm understanding and hands-on experience on IP Integration, RTL signoff tools and CDC/RDC/Lint/Synthesis
- Scripting languages (Shell, TCL, PERL, Python)
- Analog Behavioral Models (Verilog-A, Verilog-AMS, Wreal, SystemVerilog, EEnet)
- Experience with Multiple Power and Clock domains
- Experience with high-speed (Multi-GHz) digital design
- Experience with digital design of signal processing functions as: sample rate converters (integer SRC and arbitrary SRC), FIR filters, delta-sigma modulators, clock recoveries,…
- Experience with SystemC synthesis tools (Stratus HLS,…) would be an asset
Work conditions
- Caen, Toulouse, Sophia-Antipolis (Valbonne)
- on-site
- hybrid
- remote
Technologies used
- IP Integration
- RTL signoff tools
- CDC/RDC/Lint/Synthesis
Programming languages
- Shell
- TCL
- PERL
- Python
Tools used
- Verilog-A
- Verilog-AMS
- Wreal
- SystemVerilog
- EEnet
- Stratus HLS
Nice to Have
- Good communication and interpersonal skills working in a highly collaborative team
- Self-Driven with a can-do attitude
Salary
Not provided
How to Apply
Please apply via the link provided: