Conditions
Language
- English
Experience
Minimum level: Senior LevelJob Description
Lead the design and evolution of verification environments for advanced wireless technologies within Ceva's Wireless Internet of Things Business Unit.
Responsibilities
- Lead the design in System Verilog of a new verification environment checker and test bench.
- Take responsibility for the verification process, improving performance and quality of existing platforms and flows for standalone or combo IPs.
- Guide and coordinate the work of a junior engineer with potential future growth of the team.
Job Description
Ceva Inc., a leader in the Smart Edge revolution, offers a unique opportunity to shape the future of connected devices as a Verification Team Leader within its Wireless Internet of Things group in Belgrade, Serbia. The ideal candidate will lead the design and evolution of verification environments for our advanced wireless technologies, including Bluetooth, Wi-Fi, UWB, and 5G Cellular IoT, which are integrated into over a Billion devices annually. Responsibilities: * Lead the design in System Verilog of a new verification environment checker and test bench. * Take responsibility for the verification process, improving performance and quality of existing platforms and flows for standalone or combo IPs. * Guide and coordinate the work of a junior engineer with potential future growth of the team. Requirements: * B.Sc./M.Sc. in Electrical Engineering from a leading institute. * At least 8 years of proven experience in hands-on ASIC verification, including test bench development, test case creation, and Coverage closure. * At least 3 years of prior experience in technical leadership of a small team of engineers. * Strong knowledge of UVM and industry-standard verification methodologies. * Excellent communication skills. * Excellent problem-solving and debugging skills. * Fluent English - Verbal and Writing Advantages: * Knowledge of communication protocol.
Qualifications
- B.Sc./M.Sc. in Electrical Engineering from a leading institute
- At least 8 years of proven experience in hands-on ASIC verification, including test bench development, test case creation and Coverage closure
- At least 3 years of prior experience in technical leading a small team of engineers
- Strong knowledge of UVM and industry-standard verification methodologies
- Excellent communication skills
- Excellent problem-solving and debugging skills
- Fluent English - Verbal and Writing
Work conditions
- on-site
- hybrid
- remote
Technologies used
- Bluetooth
- Wi-Fi
- UWB
- 5G Cellular IoT
Tools used
- UVM
- System Verilog
Salary
Not provided